1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. Particularly, the present invention is suitable for manufacturing a transistor.
2. Background Art
A generally practiced conventional method for manufacturing a transistor will be described.
First, a polycrystalline silicon (poly-Si) film that becomes the material for a gate electrode is deposited, and appropriate ions are implanted therein. Thereafter, the poly-Si film is processed to have the shape of the gate electrode; impurity ions are implanted into an area to become a source-drain extension (hereafter briefly referred to as extension) using the poly-Si gate electrode as a mask; and annealing is performed for activating the impurity using a flash lamp. Next, a gate sidewall is formed, and then, ions are implanted into areas to become source-drain regions using the poly-si gate electrode and the sidewall as masks. Here, in order to sufficiently diffuse the impurity implanted in the poly-si gate electrode, heat treatment, such as RTA (rapid thermal annealing) is performed. Then, annealing is further performed for activating the impurity implanted in the source-drain regions and the gate electrode using a flash lamp.
In the above-described method, the reason why an impurity is implanted into poly-Si, which is the material for the gate electrode, is to control the work function of the gate electrode, and to lower the threshold voltage. In order to lower the threshold voltage, it is desirable that the gate electrode is doped with a large quantity of the impurity and this impurity is diffused in the gate electrode. Therefore, in the above-described method, it is considered that the heat treatment using RTA for diffusing the impurity is performed at a temperature of about 800° C. or above for several seconds.
On the other hand, in the source-drain region, a shallow junction of the diffusion region is desired. Here, in order to form a shallow diffusion region, ion implantation at a low acceleration, and the optimization of the annealing treatment for activating the impurity after ion implantation, are important. Specifically, when the annealing treatment after ion implantation is performed at a high temperature and for a short time, the impurity is diffused inwardly and outwardly. On the other hand, if the annealing temperature is lowered for preventing diffusion, the impurity cannot be sufficiently activated. Therefore, as a method for instantaneously supplying energy required for activation, annealing using a flash lamp is used also in the above-described method for forming a transistor. The use of the flash lamp enables light emitting within the range between several hundred microseconds and several milliseconds, and the activation of the impurity without changing the distribution of implanted impurity ions.
Here, as a method for accurately controlling the profile of the impurity, implantation of Ge (germanium) ions before or after implanting B (boron) ions has also been considered (e.g., refer to Japanese Patent Application Laid-Open No. 2003-309079)
However, as described above, in order to sufficiently diffuse the impurity ions in the gate electrode, heat treatment with RTA must be performed at 800° C. or above for several seconds. However, if heat treatment is performed under such conditions, it is considered that the impurity implanted into the extension may be redistributed, or at least the impurity activated by flash-lamp annealing may be inactivated.
It is also considered that the impurity implanted into the source-drain region is diffused by RTA; therefore, the punch through between the source and the drain must be prevented. Therefore, the width of the gate sidewall must be sufficiently enlarged, causing a problem in a semiconductor device requiring miniaturization.
Although flash-lamp annealing is performed after RTA for activating the impurity in the source-drain region, if flash-lamp annealing is performed in the state having stress of the Si substrate produced during RTA, a defect such as slipping may occur in the Si substrate, or the Si substrate may be damaged.